瑞芯微RK3576芯片详细规格参数Datasheet

RK3576是瑞芯微旗下一款低功耗、高性能的通用型SoC处理器，适用于基于ARM的PC和边缘计算设备、个人移动互联网设备和其他数字多媒体应用，采用Arm架构的八核心CPU，集成GPU、MCU、NPU、VPU等多种计算核心，具有丰富的外设接口，可以满足AIoT中的复杂场景需求。以下是RK3576的详细规格参数datasheet，方便行业客户参考选型。

RK3576视频解码器支持H.264、H.265、VP9、AV1、AVS2等，最高支持8K@30fps或4K@120fps，视频编码器支持H.264和H.265，最高支持4K@60fps，高质量JPEG编码器/解码器最多支持4K@60fps。嵌入式3D GPU使RK3576与OpenGL ES 1.1、2.0和3.2、OpenCL 2.0及Vulkan 1.1完全兼容。带有MMU的专用2D硬件引擎将最大限度地提高显示性能，并提供非常平稳的操作。
RK3576引入了新一代1600万像素ISP（图像信号处理器）。它实现了许多算法加速器，如HDR、3A、CAC、3DNR、2DNR、锐化、去雾、增强、Debayer、小角度镜头失真校正等。
内置NPU支持INT4/INT8/INT16/FP16/BF16/TF32混合操作。此外，由于其强大的兼容性，基于TensorFlow/MXNet/PyTorch/Caffe等一系列框架的网络模型可以轻松转换。

RK3576支持高性能双通道外部存储器接口（LPDDR4/LPDDR4X/LPDDR5），能够维持苛刻的存储器带宽，还提供了一套完整的外围接口，以支持非常灵活的应用。

1.2.1 Microprocessor
 Cortex A72 cluster
 Quad Cortex A72 MPCore processor
 48kB L1 instruction cache and 32kB L1 data cache for each core
 1MB unified L2 cache
 Cortex A53 cluster
 Quad Cortex A53 MPCore processor
 32kB L1 instruction cache and 32kB L1 data cache for each core
 512kB unified L2 cache
RK3576 Datasheet Rev 1.0 by SCENSMART
 TrustZone technology
 ARMv8 Cryptography Extensions
 Full implementation of the ARM architecture v8-A instruction set, ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerating media and signal processing
 Two isolated voltage domains to support DVFS, one is for A72 cluster and the other is for A53 cluster.
 Independent power domain for each CPU core system (CPU+Neon+FPU+L1 cache).
1.2.2 Memory Organization
 Internal on-chip memory
 BootRom
 Supports system boot from the following devices:
 FSPI interface
 eMMC interface
 UFS interface
 SD card interface
 USB interface
 Supports system code download by the following interface:
 USB OTG interface
 PMU_SRAM (32kB) is for low power application
 SYS_SRAM (512kB) may be shared by any on-chip components
 External off-chip memory
 Dynamic Memory interface
 JEDEC standards LPDDR4/LPDDR4X-4266 and LPDDR5-4800.
 Dual channels, each channel has 16bits data width.
 Up to 2 ranks (chip select) for each channel.
 Up to 16GB addressing space totally.
 Low power mode including power-down and self-refresh with power-down.
 eMMC interface
 Compliance to JEDEC eMMC v5.1 specification
 Compatible to eMMC 4.51 and earlier versions specification.
 Supports HS400, HS200, DDR50 and legacy operating modes
 Supports data bus width: 1-bit, 4-bit or 8-bit
 SD/MMC interface
 Compliance to SD v3.0, MMC v4.51
 Supports 4-bit data bus
 UFS interface
 Compatible to UFS v2.0 specification
RK3576 Datasheet Rev 1.0 by SCENSMART
 Supports 2 data lanes
 Up to High-Speed Gear 3 (HS-G3)
 Flexible Serial Flash Interface(FSPI)
 Supports serial NOR, NAND, pSRAM, SRAM devices
 Supports 1-bit, 2-bit, and 4-bit data width
 Supports 2 chip selects for 1-bit, 2-bit, 4-bit FSPI
1.2.3 System Component
 MCU
 Single core Cortex M0
 16kB unified I/D cache
 Programmable Interrupt Controller
 JTAG interface for debug
 CRU (clock & reset unit)
 Supports 12 PLLs to generate all clocks totally
 Supports one 24MHz oscillator as input
 Supports clock gating control for individual components
 Supports global soft-reset control for whole chip, also individual soft-reset for each component
 PMU (power management unit)
 Supports multiple configurable work modes to save power consumption with different frequency or automatic clock gating control or power domain control
 Supports many wakeup sources in different working state
 Supports 7 separate voltage domains
 Supports 30 separate power domains, which can be power up/down by software based on different application scenes
 Timer
 Supports 12 secure timers with 64bits counter and interrupt-based operation
 Supports 18 non-secure timers with 64bits counter and interrupt-based operation
 Supports two operation modes: free-running and user-defined count for each timer
 Supports timer work state checkable
 PWM
 Supports 16 on-chip PWMs (PWM0_CH0~PWM0_CH1, PWM1_CH0~PWM1_CH5,PWM2_CH0~PWM2_CH7) with interrupt-based operation
 Supports input capture mode
 PWM0 and PWM2 support IR power key capture mode
 Supports continuous mode and one-shot output mode
 PWM1 supports generates waveform through lookup table
 PMW2 supports IR transmission in NEC with full repeat, NEC with simple repeat,TC9012 or SONY mode

RK3576 Datasheet Rev 1.0 by SCENSMART
 PWM1 supports clock frequency meter
 PWM1 supports clock counter
 PWM1 and PWM2 support biphasic counter
 Supports two-stage frequency division of working clock
 Watchdog
 Supports 5 non-secure watchdog and 1 secure watchdog
 32-bit watchdog counter
 Counter counts down from a preset value to 0 to indicate the occurrence of a timeout
 WDT can perform two types of operations when timeout occurs:
 Generate a system reset
 First generate an interrupt and if this is not cleared by the service routine by the time a second timeout occurs then generate a system reset
 Interrupt Controller
 Supports 4 PPI interrupt source and 480 SPI interrupt sources input from different components inside SoC
 Supports 16 software-generated interrupts
 Input interrupt level is fixed, high-level sensitive for SPI and low-level sensitive for PPI
 Supports different interrupt priority for each interrupt source, and they are always software-programmable
 DMAC
 Supports 3 DMA controllers for peripheral system
 Supports Linked list DMA mode to complete scatter-gather transfer
 Supports data transfer types including memory-to-memory, memory-to-peripherals and peripherals-to-memory
 Each DMAC features:
 Supports 8 channels
 Supports 32 hardware request from peripherals
 Supports 2 interrupt output
 Supports TrustZone technology and programmable secure state
 Secure System
 Supports one cipher engine
 Supports 3 software interfaces including secure world, non-secure world and key-ladder world
 Supports Link List item (LLI) DMA transfer
 Supports symmetric and Hash algorithm lockstep error monitoring
RK3576 Datasheet Rev 1.0 by SCENSMART
 Supports symmetric algorithm anti side channel attack
 Supports Symmetrical algorithms
 AES-128, AES-192, AES-256, DES, 3DES, SM4
 ECB/CBC/OFB/CFB/CTR/CTS/XTS/CCM/GCM/CBC-MAC/CMAC mode for AES and SM4
 ECB/CBC/OFB/CFB mode for DES/TDES
 Hash algorithm
 SHA-1, SHA-256/224, SHA-512/384, SHA-512MD5, SM3 with hardware padding
 HMAC of SHA-1, SHA-256, SHA-512, MD5, SM3 with hardware padding
 Asymmetrical algorithms
 RSA (up to 4096 bits), ECC (up to 256 bits), SM2
 Key-ladder(KL)
 Supports obtaining the root key from OTP or RKRNG and deriving it
 Supports write out root key or derived key to some specific modules
 Number of stages can be configured
 Supports data scrambling for all DDR types
 Supports secure OTP
 Supports secure debug
 Supports secure DFT test
 Supports secure OS
 Except CPU, the other masters in the SoC can also support security and nonsecurity mode by software-programmable
 Some slave components in SoC can only be addressed by security master and the other slave components can be addressed by security master or non-security master by software-programmable
 System SRAM (share memory), part of space is addressed only in security mode
 External DDR space can be divided into 16 parts; each part can be softwareprogrammable to be enabled by each master
 Mailbox
 Supports one Mailbox with 14 channels in SoC to provide communication service between CPU and MCU
 Supports independent interrupt in each Mailbox channel
1.2.4 Video Codec
 Video Decoder
 Supports video decoder of H.264, H.265, VP9, AV1 and AVS2
 Supports MMU
 Supports multi-stream decoding in parallel
RK3576 Datasheet Rev 1.0 by SCENSMART
Decoder Profile Level Resolution
H.264/AVC main10 L5.2 up to 4K@60fps
H.265/HEVC main10 L6.0 up to 8K@30fps or 4K@120fps
VP9 profile 0/2 L6.0 up to 8K@30fps or 4K@120fps
AVS2 profile 0/2 L8.2.120 up to 8K@30fps or 4K@120fps
AV1 main10 L6.0 up to 8K@30fps or 4K@120fps
 H264 MVC is up to 4K@60fps
 Video Encoder
 Supports H.265 and H.264.
 Supports up to 4K@60fps.
 Supports multi-stream encoding
 JPEG Encoder
 Supports Baseline (DCT sequential)
 Supports image size is from 16×16 to 65520×65520
 Supports MJPG up to 4K@60fps
 Supports YUV400/ YUV420/YUV422/YUV444
 JPEG Decoder
 Supports image size is from 48×48 to 65520×65520
 Supports MJPG up to 4K@60fps
 Supports YUV400/YUV411/YUV420/YUV422/YUV440/YUV444
1.2.5 Neural Process Unit
 Rockchip NPU engine:
 6 TOPS* for INT8
 Supports dual core and support dual core co-work, or work independently
 Supports INT4, INT8, INT16, FP16, BF16 and TF32 operation
 Supports 1MB internal SRAM
 Supports multi-task, multi-scenario in parallel
 Supports deep learning frameworks: TensorFlow, Caffe, Tflite, Pytorch, Onnx NN,Android NN, etc.
* Sparsity
1.2.6 Graphics Engine
 3D Graphics Engine
 ARM Mali G52 MC3 GPU
 OpenGL ES 1.1, 2.0, and 3.2
 Vulkan 1.1
 OpenCL 2.0 Full Profile
 AFBC (ARM Frame Buffer Compression)
 2D Graphics Engine (RGA)
RK3576 Datasheet Rev 1.0 by SCENSMART
 Rockchip RGA v2.5 engine with dual core
 Max resolution: 8192×8192 source, 4096×4096 destination
 Block transfer and Transparency mode
 Color fill with gradient fill, and pattern fill
 Alpha blending including global alpha, per pixel alpha and fading
 Arbitrary non-integer scaling ratio from 1/16 to 16
 0, 90, 180, 270-degree rotation, x-mirror, y-mirror & rotation operation
 VDPP (Video & Display Post Process)
 Deinterlace
 Input data format: YUV420/YUV422, P/SP
 Output data format: YUV420/YUV422, SP
 Supports algorithms including I5O2, I5O1, I2O2, I1O1 and so on
 Resolution is up to 1920×1080
 Post Process
 Input data format: YUV420SP
 Output data format: YUV420/YUV444 SP
 DMSR: De-Mosquito noise, De-Ringing effect and De-Shooting effect
 ZME: Zoom Manage Engine (Video resize based Multi-Phase Algorithm)
 DCI-HIST: Histogram of Dynamic Contrast improvement
 SHARP: Sharpness
 ES: Edge Smoothing
1.2.7 Video Input Interface
 MIPI CSI-2 interface
 Supports 5 CSI-2 interfaces
 4 ports support 2 D-PHY v1.2 data-lane with 2.5Gbps/lane
 These 4 ports may be bound as 2 ports with 4 data-lane per port
 1 port supports 4 D-PHY data-lane or 3 C-PHY trios
 D-PHY is v2.0 which lane speed is 4.5Gbps
 C-PHY is v1.1 which trio speed is 2.5Gsps
 Each port supports 4 virtual channels
 DVP interface
 8/10/12/16-bit, up to 150MHz I/O frequency
 BT.601/BT.656 and BT.1120 VI interface
 Supports the polarity of pixel_clk, hsync, vsync configurable
 Supports 2/4 mux byte interleave format for BT.656/BT.1120
 Supports dual-edge sampling for BT.656/BT.1120
1.2.8 Image Signal Processor
 Video Capture (VICAP)
RK3576 Datasheet Rev 1.0 by SCENSMART
 Supports BT.601 RAW8/10/12 YUV422 8-bit input
 Supports BT.656 YUV422 8-bit progressive/interlaced input
 Supports BT.1120 YUV422 16-bit progressive/interlaced input
 Supports 2/4 mux byte interleave format for BT.656/BT.1120
 Supports dual-edge sampling for BT.656/BT.1120
 Supports receiving five groups of MIPI CSI interfaces, up to four IDs for each group
 Supports VC/DT configurable for each ID
 Supports MIPI CSI data formats: RAW8/10/12/14/16, RGB888, YUV422 8bit,YUV422 8bit interlaced, YUV420 8bit, Legacy YUV420 8bit
 Support three modes of MIPI CSI HDR: virtual channel mode, identification code mode, line counter mode
 Support window cropping
 Supports 8/16/32 times down-sampling for RAW data
 Supports RAW 2×2 binning
 Supports pixel extraction from 2×2 pattern
 Supports UV mean down sampling for YUV422
 Supports reducing frame rate
 Supports compact/non-compact output format for RAW data
 Supports NV16/NV12/YUV400/YUYV output format for YUV data
 Supports virtual stride when write to DDR
 Supports DMA burst gather 2/4/8
 Supports MMU
 Supports QOS(hurry/press)
 Supports sending RAW data directly to ISP
 Supports soft reset, auto-reset when DMA error
 Supports debug mode
 Image Signal Processor V3.9
 One channel ISP, 16M pixels
 VICAP/DMA input: raw8/raw10/raw12/raw16
 RGB-IR sensor input
 3A: include AE/Histogram, AF, AWB statistics output
 BLC: Black Level Correction
 PDAF: Phase Detection Auto Focus
 DPCC: Static/Dynamic defect pixel cluster correction
 LSC: Lens shading correction
 HDR: 2-Frame Merge into High-Dynamic Range
 DRC/TMO: Dynamic Range Compression, Tone mapping in RGB field
 Supports up to 120dB HDR with 20-bit data width
RK3576 Datasheet Rev 1.0 by SCENSMART
 EXPANDER: Sensor expander
 GIC: Green Imbalance Correction
 Debayer: Advanced Adaptive Demosaic with Chromatic Aberration Correction(CAC)
 CCM/CSM: Color correction matrix; RGB2YUV etc.
 Gamma: Gamma out correction
 Dehaze/Enhance: Automatic Dehaze and edge enhancement
 Bay3DNR: Advanced Temporal Noise reduce in RAW;
 YUVME: Noise Motion Estimate and Motion Compensation in YUV
 2DNR: Advanced Spatial Noise reduce in YUV;
 Sharp: Picture Sharpening & Edge Enhance in YUV;
 CGC: Color Gamut Compression, YUV full range/limit range convert
 3DLUT: 3D-Lut Color Palette for Customer;
 LDCH: Lens-distortion in the horizontal direction;
 LDCV: Lens-distortion in the vertical direction;
 Gain: Image local gain
 Output Scale*2: support scale down level;
1.2.9 VPSS
 VPSS
 Offline DMA input:
 Line RGB888/ARGB888/RGB565/YUV422/YUV420 SP 8bits
 Tile4x4 YUV422/YUV420 8bits (Rotate 90/180/270)
 RKFBCD64x4 YUV422/YUV420 8bits
 Online ISP input
 Both DMA and ISP input
 Maximum input: 4672×3504 (width no more than 4672)
 Minimum input: 32×32
 MIRROR: Horizontal Mirror
 CMSC: Cover or Mosaic in 8 areas
 CROP: 4 channels Crop
 Channel0 output:
 SCALE: Poly-phase filter
 ASPT_RATIO: aspect-ratio for image boundary extension
 Either Line YUV422/YUV420 SP 8bits or Tile4x4 YUV422/YUV420 8bits
 Flip: Vertical Flip
 Channel1 output:
 SCALE: Bilinear filter
 ASPT_RATIO: aspect-ratio for image boundary extension
 Either Line RGB888/ARGB888/RGB565/YUV422/YUV420 SP 8bits or Tile4x4 YUV422/YUV420 8bits
 Flip: Vertical Flip
 Channel2 output:
 SCALE: Bilinear filter, Maximum output: 1920×1080 (width no more than 1920)
 ASPT_RATIO: aspect-ratio for image boundary extension
 Line YUV422/YUV420 SP 8bits
 Flip: Vertical Flip
 Channel3 output:
 SCALE: Bilinear filter, Maximum output: 1920×1080 (width no more than 1920)
 ASPT_RATIO: aspect-ratio for image boundary extension
 Line YUV422/YUV420 SP 8bits
 Flip: Vertical Flip
 Either channel0 or channel1 Tile4x4 output
1.2.10 Video Output Processor
 Video Port
 Video Port0 supports up to 4K@120Hz with 10-bit data
 Video Port1 supports up to 2560×1600@60Hz with 10-bit data
 Video Port2 supports up to 1920×1080@60Hz with 8-bit data
 Each Video Port may connect to any of HDMI/eDP/DP/DSI-2
 Port1 and Port2 may connect to parallel output interface
 Data format
 Raster:
 ARGB8888/RGB8888/RGB565
 YUV420/YUV422/YUV444, 8/10-bit
 YUV444i
 Tile 4×4
 YUV420/YUV422/YUV444, 8/10-bit
 FBCD 32×8 split (GPU)
 RGB565/RGBA1010102/RGB888/RBGA8888
 FBCD 64×4 (Video)
 RGB565/RGBA1010102/RGB888/RBGA8888
 YUV420/YUV422/YUV444, 8/10-bit
 Display Layer
 Supports two type of display layers (Cluster and eSmart)
 FBCD data is only supported in cluster layer
 Layer split is only supported in cluster layer
 Multi-region is only supported in eSmart layer
 Supports Data swap, replication, offset, virtual display
RK3576 Datasheet Rev 1.0 by SCENSMART
 Supports scaling down/up with ratio is 1/4~8
 Supports CSC (Color Space Convert) for BT601/BT709/BT2020
 Cluster layer
 Supports 2 cluster layers
 Supports resolution is up to 4kx2k
 Supports FBC 32×8 and FBC 64×4
 Supports rotation
 eSmart layer
 Supports 4 eSmart layers
 Supports resolution is up to 4kx2k
 Supports 4 region in each layer
 Overlay
 Supports Layer position exchange
 Supports transparency color key and 8BPP alpha blending
 Supports per-pixel alpha, pre-multiplied alpha and global alpha
 Supports RGB or YUV domain overlay
 Post Process
 Supports HDR10/HLG/HDR Vivid
 Supports Post scale
 Supports Dither down
 Supports CSC, color domain and color range convert.
 Supports Gamma/3D-LUT
 Supports ACM, auto color management
 Supports DCI, dynamic contrast improvement
 Supports SHARPNESS
 Write Back
 Output data format: XRGB8888/RGB888/RGB565/YUV420
 Max resolution: 1920×1080
 Support virtual stride
 Supports automatic write back and one frame write back model
 Supports horizontal scale
1.2.11 Display interface
 HDMI/eDP TX interface
 One HDMI/eDP TX combo interface
 HDMI interface
 HDMI v2.1
 Supports up to 4K@120Hz
 Output data format: RGB/YUV444/YUV422/YUV420 8/10-bit
RK3576 Datasheet Rev 1.0 by SCENSMART
 Supports CEC (Consumer Electronic Control) and ARC (Audio Return Channel)
 HDCP v2.3 and HDCP v1.4
 eDP interface
 eDP v1.3 and compliant with DisplayPort v1.2
 Main link containing 4 physical lanes
 Each lane supports RBR(1.62Gbps), HBR(2.7Gbps) and HBR2(5.4Gbps)
 Supports up to 4K@60Hz
 Output data format: RGB/YUV444/YUV422 8/10-bit
 Supports HDCP v1.3
 Supports PSR (Panel Self Refresh)
 Supports I2S (up to 8 channels) and S/PDIF audio interface
 Supports AUX and reading of the display EDID
 DisplayPort TX and USB combo interface
 Supports one USBDP combo PHY
 Supports USB3.2 Gen1x1 and DisplayPort v1.4
 Supports 4 transmission data lanes
 Supports USB Type-C AltMode
 DisplayPort TX controller
 DisplayPort v1.4
 Supports 1/2/4 lanes with lane speed including 1.62、2.7、5.4 and 8.1Gbps
 Supports up to 4K@120Hz
 Output data format: RGB/YUV444/YUV422/YUV420 8/10-bit
 Supports Multi-Stream Transport (MST) with 3 displays
 Supports DP AltMode on USB Type-C
 Supports HDCP v2.3 and HDCP v1.3
 USB controller
 Supports USB3.2 Gen1x1
 Supports Dual-Role Device (DRD)
 Supports xHCI Host with up to 64 devices
 MIPI DSI-2 TX interface
 One MIPI DSI-2 v1.1 interface with D-PHY v2.0 or C-PHY v1.1
 Supports 4 data lanes on D-PHY
 Supports 3 data trios on C-PHY
 Supports up to 2560×1600@60Hz
 Supports RGB (up to 10bit) data format
 Parallel output interface
 Supports RGB/BT.656/BT.1120
 Supports up to 1920×1080@60Hz
RK3576 Datasheet Rev 1.0 by SCENSMART
 Supports RGB (up to 8bit) format
 EBC output interface
 Supports E-ink EPD (Electronic Paper Display)
 Supports up to 2560×1920 with hardware decoding
 Supports data bus with 16-bit width
 Supports up to 32 level gray scale
 Supports Direct mode、LUT mode and 3-window mode
 Supports window display mode
1.2.12 Serial Audio Interface (SAI)
 Supports five SAI interfaces
 SAI 0/1 support 4 TX lanes and 4 RX lanes
 SAI 2/3/4 support 1 TX lane and 1 RX lane
 Supports I2S/TDM/PCM mode
 Supports 3 I2S formats (normal, left-justified, right-justified)
 Supports master and slave work mode, software configurable
 Supports 4 PCM formats (early, late1, late2, late3)
 Supports TDM normal, 1/2 cycle left shift, 1 cycle left shift, 2 cycle left shift, right shift mode serial audio data transfer
 Supports sample rate is up to 192KHz
 Supports audio resolution is from 16bits to 32bits
 SPDIF TX
 Two SPDIF TX ports
 Supports two 16-bit audio data store together in one 32-bit wide location
 Supports bi-phase format stereo audio data output
 Supports 16 to 31-bit audio data left or right justified in 32-bit wide sample data buffer
 Supports 16, 20, 24 bits audio data transfer in linear PCM mode
 Supports non-linear PCM transfer
 SPDIF RX
 Two SPDIF RX ports
 Supports one internal 30-bit wide and 32-location deep FIFO for receiving audio data
 Supports combined interrupt output
 Supports DMA handshaking interface and configurable DMA water level
 Supports liner PCM(IEC60958) and non-liner PCM(IEC61937)
 Supports 16~24 bits audio sample length for liner PCM application
 Supports 16 bits audio sample length for non-liner PCM application
 Supports up to 384kHz sample rate with the corresponding reference clock equal to384KHz*64*2*10, that is 491.52MHz
 Supports the frequency of reference clock is at least 10 times the frequency of the bi-phase encoding clock, but not more than 256 times
 Supports recovering clock and audio data from input bit-stream
 PDM0/PDM1
 Supports up to 8 channels
 Supports resolution is from 16bits to 24bits
 Supports sample rate is up to 192KHz
 Supports PDM master receive mode
 Supports gain control
 ASRC
 Supports dual 2-channel ASRC and dual 4-channel ASRC
 Supports fixed length conversion mode and real time conversion mode
 Supports asynchronous sample rate clock for real time conversion mode
 Digital Audio Codec
 Support 2 channels digital DAC
 Support I2S/PCM interface, master and slave mode
 Support 16-bit sample resolution
 Support three modes of mixing for every digital DAC channel
 Support volume control
1.2.13 Connectivity
 SDIO interface
 SDIO v3.0
 4-bit data bus widths
 GMAC 10/100/1000M Ethernet controller
 Supports two Ethernet controllers
 Supports IEEE 802.3 10/100/1000 Mbps Ethernet MAC with RGMII or RMII
 Supports both full-duplex and half-duplex operation
 Combo high speed interface
 Supports one combo PCIe2.1/SATA3.1 interface with one data lane
 Supports one combo PCIe2.1/SATA3.1/USB3.2 Gen1x1 interface with one data lane
 USB2.0 port is disabled also when USB3.2 Gen1x1 is disabled.
 PCIe interface
 Supports PCIe v2.1
 Supports Root Complex(RC) only
 Supports up to 5GT/s data rate
 SATA interface
 Supports SATA v3.1 and AHCI revision v1.3.1
RK3576 Datasheet Rev 1.0 by SCENSMART
 Supports eSATA
 Supports up to 6GT/s data rate
 USB interface
 Supports USB3.2 Gen1x1 with USB v2.0
 Supports DRD (host and device)
 Supports up to 5Gbps data rate
 Supports xHCI Host with up to 64 devices
 SPI interface
 5 SPI ports
 Supports two chip-select in each interface
 Supports serial-master and serial-slave mode, software-configurable
 I2C interface
 10 I2C ports in Master mode
 Supports 7-bit and 10-bit address mode
 Software programmable clock frequency
 Supports data rate is up to 100kbps in the Standard-mode and si up to 400kbps in the Fast-mode
 I3C interface
 2 I3C master ports
 Compliance with I2C
 Supports SDR mode
 Supports In-Band interrupt（IBI）
 Supports hot-join onto I3C bus
 Supports dynamical and static slave address assigned
 Supports up to 10 devices
 Supports error detection (CE0~CE2)
 UART interface
 12 UART ports
 Embedded two 64-byte FIFO for TX and RX operation respectively
 Supports 5bit, 6bit, 7bit, 8bit serial data transmit or receive
 Standard asynchronous communication bits such as start, stop and parity
 Supports different input clock for UART operation to get up to 8Mbps baud rate
 UART1~UART11 support auto flow control mode
 UART1-UART11 support RS485 function
 CAN interface
 2 CAN ports
 Compliance to CAN and CAN FD specification
 Supports CAN standard and extended frame
RK3576 Datasheet Rev 1.0 by SCENSMART
 Supports data frame, remote frame, overload frame, error frame and frame interval
 Supports 8192-bit receive FIFO
 DSMC interface
 Supports up to select 4 chips, and the selecting signals could be configured to be valid simultaneously in the write transaction
 Supports 8-wire and 16-wire serial transfer mode
 Supports configurable write/read contiguous address merging transaction
 Supports configurable write/read boundary address splitting transaction
 Supports to transform WRAP transfer to INCR transfer
 Supports configurable serial address width: 16 bits or 32 bits
 Supports 3 clock mode: normal mode, always-on mode, no-edge-clk mode
 Supports to request DMAC to transfer data when receiving an interrupt
 FlexBus interface
 Supports built-in DMA and ping-pong operation for allocating two address
 Supports transmission and receiving mode
 Supports clock port two modes, free running and following data mode
 Supports configurable four possible combinations for the clock polarity and phase
 Supports single mode and continuous mode
1.2.14 Others
 Multiple group of GPIO
 All of GPIOs can be used to generate interrupt
 Supports level trigger and edge trigger interrupt
 Supports configurable polarity of level trigger interrupt
 Supports configurable rising edge, falling edge and both edge trigger interrupt
 Supports configurable pull direction (a weak pull-up and a weak pull-down)
 Supports configurable drive strength
 Temperature Sensor (TS-ADC)
 Supports User-Defined Mode and Automatic Mode
 In User-Defined Mode, start_of_conversion can be controlled completely by software, and also can be generated by hardware.
 In Automatic Mode, the temperature of alarm (high/low temperature) interrupt can be configurable
 In Automatic Mode, the temperature of system reset can be configurable
 Supports 6-channel TS-ADC with the temperature criteria can be configurable
 -40~125°C temperature range and 1°C temperature resolution
 Successive approximation ADC (SARADC)
 Supports 12-bit resolution
RK3576 Datasheet Rev 1.0 by SCENSMART
 Supports up to 1MS/s sampling rate
 Supports 8 single-ended input channels
 OTP
 Supports 16-kbit space and higher 4kbit address space is non-secure part.
 Supports read and program word mask in secure model
 Supports maximum 32 bit OTP program operation
 Supports maximum 16 word OTP read operation
 Program and Read state can be read
 Program fail address record
 Package Type
 FCCSP698L (body: 16.1mm x 17.2mm; ball size: 0.30mm; ball pitch:0.55mm&0.60mm&0.65mm mixed)

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