瑞芯微RK1820大算力AI边缘计算协处理器详细规格参数datasheet

RK1820 是一款面向机器视觉应用，特别是人工智能（AI）相关应用的高性能机器视觉协处理器 SoC。它基于三个独立的 64 位 RISC-V 内核（含 FPU 浮点单元），每个内核配备 32KB 指令缓存 (I-Cache)、32KB 数据缓存 (D-Cache) 以及 128KB 二级缓存 (L2 Cache)。

其内置 NPU 支持 INT4/INT8/INT16/FP8/FP16/BF16 混合精度运算，算力高达 20 TOPs。此外，凭借其强大的兼容性，可轻松转换基于 TensorFlow/MXNet/PyTorch/Caffe 等一系列框架的网络模型。

RK1820 内置极高带宽的 DRAM。同时，为与主处理器通信，该芯片还集成了两个 PCIe 2.0 和 USB 3.0 组合式 PHY。

1.2.1 Application Processor

Three RISC-V cores abbreviated as SRV, VRV0 and VRV1
SRV is implemented with RV64GCB ISA and VR0/VRV1 is implemented with RV64GCBV ISA
All cores are integrated FPU with RISC-V H/F/D precision
Each core has 32KB L1 I-Cache, 32KB L1 D-Cache and 128KB L2 cache
VRV0 and VRV1 is integrated with 128-bit vector unit

1.2.2 Memory Organization

Internal on-chip memory
- Bootrom
  - Support system boot from the following device:
    - SPI interface
    - eMMC interface
    - SD/MMC interface
  - Support system code download by the following interface:
    - 0 interface
    - UART interface
    - PCIe interface
  - 512KB system SRAM
  - Build-in Dynamic Memory Interface
    - Capacity is 5GB

External off-chip memory
- Combo SDMMC Interface, work at only one of the following modes
  - eMMC
- Fully compliant with JEDEC eMMC 4.51 specification
- Support HS200, but not support CMD Queue
- Support three data bus width mode: 1bit, 4bits and 8bits
  - SD/MMC Interface
- Compatible with SD3.0, MMC 51
- Support 1bit, 4bits data bus width
  - SDIO Interface
- Compatible with SDIO3.0 protocol
- 4-bit data bus widths

Flexible Serial Flash Interface (FSPI)
- Support transfer data from/to serial flash device
- Support 1bit, 2bits or 4bits data bus width
- Support 2 chips select

1.2.3 System Component

CRU (clock & reset unit)
- Support total 4 PLLs to generate all clocks
- One oscillator with 24MHz clock input
- Support clock gating control for individual components
- Support global soft-reset control for whole chip, also individual soft-reset for each component

PMU (power management unit)
- Multiple configurable work modes to save power by different frequency or automatic clock gating control
- Support 3 separate voltage domains VDD_TOP, VDD_LOGIC, VDD_PMU

Timer
- Support 6 timers with 64bits counter and interrupt-based operation
- Support two operation modes: free-running and user-defined count for each timer
- Support timer work state checkable

Watchdog
- 32-bit watchdog counter
- Counter counts down from a preset value to 0 to indicate the occurrence of a timeout
- WDT can perform two types of operations when timeout occurs:
  - Generate a system reset
  - First generate an interrupt and if this is not cleared by the service routine by the time a second timeout occurs then generate a system reset
- Three Watchdogs

Interrupt Controller
- Support 160 interrupt sources input from different components inside SoC for SRV and 64 interrupt sources input for VRV
- Support 1 software-triggered interrupt in m-mode and s-mode each
- Input interrupt level is fixed, high-level sensitive
- Support different interrupt priority for each interrupt source, and they are always software-programmable

DMAC
- Support 2 physical channels
- Support 22 groups of peripheral request interfaces
- Support 24 logic channels, each logic channel support the following feature
  - Support the data transfer of memory-to-memory, memory-to-peripherals, peripherals-to-memory
  - Support Linked list DMA function to complete scatter-gather transfer
  - Support three kinds of multi-block transfer: contiguous address, auto reload, link list

Secure System
- Support one cipher engine
  - Support Symmetrical algorithms
    - AES-128, AES-192, AES-256, SM4
    - ECB/CBC/OFB/CFB/CTR/CTS/XTS/CCM/GCM/CBC-MAC/CMAC mode for AES and SM4

Hash algorithm
- SHA-1, SHA-256/224, MD5, SM3 with hardware padding
- HMAC of SHA-1, SHA-256, MD5, SM3 with hardware padding
Asymmetrical algorithms
- RSA (up to 4096 bits), ECC (up to 256 bits), SM2
Key-ladder (KL)
- Support obtaining the root key from OTP or RKRNG and deriving it
- Support writes out root key or derived key to some specific modules
- Number of stages can be configured

Mailbox
- Twelve mailboxes in SoC used to service different RISC-V communication

1.2.4 JPEG CODEC

JPEG encoder
- Supports Baseline (DCT sequential)
- Supports JPEG file interchange format (JFIF) 02
- Supports image size is from 16×16 to 65520×65520
- Supports YUV400/YUV420/YUV422/YUV444

JPEG Decoder
- Support Baseline (DCT sequential)
- Support JPEG file interchange format (JFIF) 02
- Support image size is from 48×48 to 65520×65520
- Support YUV400/YUV420/YUV422/YUV440/YUV411/YUV444/RG888/RGB565

1.2.5 Neural Process Unit

Rockchip NPU engine:
- Up to 20 TOPS for INT8
- Support INT4/INT8/INT16/FP8/FP16/BF16 operation
- Support deep learning frameworks: TensorFlow, Caffe, Tflite, Pytorch, Onnx NN, Android NN,

1.2.6 2D Graphics Engine

2D Graphics Engine (RGA)
Data format
- SRC0 Input data format:
  - ARGB8888/RGBA8888/RGBA4444/RGBA5551
  - RGB888P/RGB565
  - YUV422-P/YUV422-SP-8bit/10bit (clip to 8bit after input)
  - YUV420-P/YUV420-SP-8bit/10bit (clip to 8bit after input)
  - YUV444I/YUV444SP-8bit
  - YVYU422-8bit
  - YUV400-8bit
  - TILE4X4 YUV420/422/444-8bit
  - TILE4X4 YUV420/422/444-10bit (clip to 8bit after input)
  - BPP1/2/4/8
- SRC1 Input data format:
  - ARGB8888/RGBA8888/RGBA4444/RGBA5551/A8
  - RGB888P/RGB565
- Output data format (all YUV format is 8bit):
  - ARGB8888/RGBA8888/ARGB4444/RGBA4444/ARGB5551/RGBA5551
  - RGB888/RGB565
  - YUV420/YUV422 P/SP
  - YUV400/Y4
  - YUV444SP/444I
- Pixel Format conversion, 601/BT.709
- Dither operation

Max resolution : 8192×8192 source, 4096×4096 destination

Scaling
- Down-scaling: Average/Bilinear filter
- Up-scaling: Bi-cubic filter(source>1992 would use Bi-linear)
- Arbitrary non-integer scaling ratio, from 1/16 to 16
Rotation
- 0, 90, 180, 270-degree rotation
- x-mirror, y-mirror operation
- Mirroring and rotation co-operation
BitBLT
- Block transfer
- Color palette/Color fill, support with alpha
- Transparency mode (color keying/stencil test, specified value/value range)
- Two source BitBLT
- A+B=B only BitBLT, A support rotate & scale when B fixed
- A+B=C second source (B) has same attribute with (C) plus rotation function
Alpha Blending
- Comprehensive per-pixel alpha (color/alpha channel separately)
- Fading
- Support SRC1(R2Y) +SRC0(YUV) -> DST(YUV)
- Support DST Full CSC convert for YUV2YUV
OSD Automatic Inversion
- Support OSD sources in ARGB8888/ARGB1555/ARGB444/ARGB2BPP format
- Support SRC0 and OSD overlay

1.2.7 Serial Audio Interface (SAI)

Support 1 SAI interfaces
- Support 4 TX lanes and 4 RX lanes
- Support audio protocol: I2S, PCM, TDM
- Support up to 128 slots available with configurable size
- Support slot length 8 to 32 bits configurable
- Support slot valid data length 8 to 32 bits configurable

1.2.8 Connectivity

MAC 10/100/1000M Ethernet
- Support one Ethernet controllers
- Support 10/100/1000-Mbps data transfer rates with the RGMII interfaces
- Support both full-duplex and half-duplex operation
- Support for TCP Segmentation Offload (TSO) and UDP Segmentation Offload (USO) network acceleration
- Support Ethernet packet timestamping as described in IEEE 1588-2002 and IEEE 1588-2008

USB 2.0 DRD (Dual-Role Device)
- Support one USB2.0 DRD (Dual-Role Device)
- Compatible with USB 2.0 specification
- Support high-speed(480Mbps), full-speed(12Mbps) and low-speed(1.5Mbps) mode
- Support Enhanced Host Controller Interface Specification (EHCI), Revision 0
- Support Open Host Controller Interface Specification (OHCI), Revision 0a

Multi-PHY Interface
- Support two multi-PHY with two PCIe2.1 controller and one USB3.0 controller (multiplex to one of the PHY)
- Support one of the following interfaces for each multi-PHY
  - 0 Host
  - 1

USB 3.0 Dual-Role Device (DRD) Controller
- Static USB3.0 Device
- Static USB3.0 xHCI host
- 0/USB2.0 OTG A device and B device basing on ID
1 interface
- Compatible with PCI Express Base Specification Revision 1
- Support one lane
- Support Root Complex (RC) mode only
- Support 2.5Gbps and 5.0Gbps serial data transmission rate per lane per direction

SPI interface
- Support 2 SPI Controllers
- Support two chip-select output
- Support serial-master and serial-slave mode, software-configurable

I2C Master controller
- Support 5 I2C ports in Master mode
- Support 7bits and 10bits address mode
- Software programmable clock frequency
- Data on the I2C-bus can be transferred at rates of up to 100k bits/s in the Standard-mode, up to 400K bits/s in the Fast-mode and up to 1M bit/s in high- speed mode

SMBus slave interface
- Support 1 independent SMBus
- Supports slave mode of SMBus bus
- Support SMBus protocol: write byte/read byte/read word/read 32 protocol/write 32 protocol/block write/block read
- Support PEC
- Support Alert
- Support directed get UDID command
- Clock stretching and wait state generation

UART interface
- Support 3 UART ports
- Embedded two 64-byte FIFO for TX and RX operation respectively
- Support 5bit, 6bit, 7bit, 8bit serial data transmit or receive
- Standard asynchronous communication bits such as start, stop and parity
- Support different input clock for UART operation to get up to 4Mbps baud rate
- Support auto flow control mode for UART2
- Support RS485 function for UART2

PWM
- Support 1 PWM interface, total 8 channels
- Support input capture mode
- Support continuous mode and one-shot output mode
- Support two-stage frequency division of working clock
- Support power key capture mode
- Support clock frequency meter
- Support clock counter

1.2.9 Others

Multiple groups of GPIO
- All of GPIOs can be used to generate interrupt
- Support level trigger and edge trigger interrupt
- Support configurable polarity of level trigger interrupt
- Support configurable rising edge, falling edge and both edge trigger interrupt
Support configurable pull direction (a weak pull-up and a weak pull-down)
Support configurable drive strength
Temperature Sensor (TS-ADC)
- Support User-Defined Mode and Automatic Mode
- In User-Defined Mode, start_of_conversion can be controlled completely by software, and also can be generated by
- In Automatic Mode, the temperature of alarm (high/low temperature) interrupt can be configurable
- In Automatic Mode, the temperature of system reset can be configurable
- Support 3 channel TS-ADC
- -40~125°C temperature range and +/-3.5°C temperature accuracy
- Resolution: 01°C

Successive approximation ADC (SARADC)
- Support 1 SARADC, each support 2 single-ended input channels
- 13-bit resolution
- Up to 2MS/s sampling rate
- Support single mode and series conversion mode